The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.
For example, light diffraction in an optical lithography system becomes an obstacle for further scaling down the feature size. Comment techniques used to decrease the light diffraction impact includes an optical proximity correction (OPC), a phase shift mask (PSM), and an immersion optical lithography system. An electron beam lithography system is another alternative to scale down the feature size. However, a large overlay error at a boundary area of two subfields may occur by using a different electron beam at a different pattern layer.
Accordingly, what is needed is a method to reduce the overlay error caused by the different electron beams used at the different pattern layers during the electron beam lithography patterning process.